1. Field of the Invention
This invention relates to computer systems, and more particularly, to a circuit topology for supporting the routing of signals to memory devices.
2. Description of the Related Art
The demand for increased computing power in computer systems is ever increasing. Such demands include the demand for faster processors, additional memory, and faster system boards. The demand for faster processors and system boards often times results in the need for faster clock speeds.
As clock speeds increase, the effects of loading may become more significant in the distribution of clock signals. FIGS. 1A and 1B each illustrate a typical circuit topology for clock distribution. In each of the embodiments shown, a memory controller 2 having a phase-locked loop (10) distributes the differential clock signal to DIMM (dual inline memory module) 20 via a point-to-point connection. Additional memory modules may be coupled to the memory controller in the same manner using separate pairs of transmission lines. Each DIMM 20 may include a resistor that is electrically coupled between the transmission lines. Thus, for each DIMM slot on the board, a separate pair of transmission lines may be required. One possible solution to this problem is to use the same pair of transmission lines for each of the DIMMs. However, if a single pair of transmission lines were used, the resistance between each transmission line of the pair would vary with the DIMM population due to the parallel connection of the termination resistors (for the embodiment shown in FIG. 1A), and hence the loading might also vary. Such a configuration could potentially lead to timing mismatches and possibly limit the maximum clock speed at which the system board upon which the DIMMs are implemented may operate.
Higher operating speeds may also subject address signals and data signals to more pronounced loading effects. FIG. 1A illustrates one circuit topology used to couple a data line from a memory controller to memory banks of a DIMM (dual-inline memory module). In the embodiment shown, transmission line L_lead-in is coupled to a first connector, while a second transmission line segment couples the first connector to a second connector. The second connector is coupled to a termination resistor RT by a third transmission line segment. The memory banks of each DIMM are coupled to the connectors by a pair of transmission line stubs with a damping resistor RD between them. Signals transmitted between the memory controller and the memory banks may be affected by parasitic inductances in the transmission lines. In particular, parasitic inductances L_stub1 and L_stub2 in the transmission line stubs of each DIMM may cause signal reflections. While the damping resistors RD and RT may absorb some of the energy, some reflected energy may still remain in the various transmission line segments. The presence of such reflected energy may limit the maximum clock speed of the memory, and thus the maximum data rate on the data bus.
FIG. 1B illustrates an alternate configuration which uses on-die termination (ODT) instead of a termination resistor RT as in the embodiment of FIG. 1A. The ODT within each memory bank (or memory chip within each bank) may eliminate the need for a termination resistor RT to be associated with each data line (or address line). However, ODT may require extra control lines between the memory controller and the individual die of the memory banks. Despite the ODT, some reflected energy may remain in the various transmission line segments. As with the embodiment shown in FIG. 1A, damping resistors may be used to absorb the reflected energy. However, the damping resistors may not be able to absorb all of the reflected energy, and thus the maximum data rate may still be limited despite any improvement over the embodiment of FIG. 1A.